On 02Jun2006 02:53PM (-0400), Michael Lorenz wrote:

> Please post the pcictl dump output for this device ( try pcictl pci0 
> dump -d 14 )

voila:

PCI configuration registers:
  Common header:
    0x00: 0x12111113 0x02900104 0x02000010 0x00004000

    Vendor Name: Accton Technology (0x1113)
    Device Name: MPX 5030/5038 Ethernet (0x1211)
    Command register: 0x0104
      I/O space accesses: off
      Memory space accesses: off
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): on
      Fast back-to-back transactions: off
    Status register: 0x0290
      Capability List support: on
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: network (0x02)
    Subclass Name: ethernet (0x00)
    Interface: 0x00
    Revision ID: 0x10
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x40
    Cache Line Size: 0x00

  Type 0 ("normal" device) header:
    0x10: 0x00001401 0xf4101000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x12111113
    0x30: 0x00000000 0x00000050 0x00000000 0x40200105

    Base address register at 0x10
      type: i/o
      base: 0x00001400, not sized
    Base address register at 0x14
      type: 32-bit nonprefetchable memory
      base: 0xf4101000, not sized
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      not implemented(?)
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x1113
    Subsystem ID: 0x1211
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0x50
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x40
    Minimum Grant: 0x20
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x05

  Capability register at 0x50
    type: 0x01 (Power Management, rev. 1.0)

  Device-dependent header:
    0x40: 0x00000000 0x00000000 0x00000000 0x00000000
    0x50: 0x76010001 0x00000100 0x00000000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x00000000
    0x70: 0x00000000 0x00000000 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000



Best regards,

-- 
Bob Bernstein