I just tried updating a machine to -current that was running 
1.6.1_STABLE.  During boot of the -current kernel, I get
"pciide0:0: bogus intr"
"pciide0:1: bogus intr"
... alternating back and forth from 0:0 to 0:1 infinitely... I guess 
that means controller 0 and channels 0 and 1.

If it's of any consequence, I'm also using software RAID.  Another 
interesting thing I noticed is that the "bogus intr" message is there 
with 1.6.1_STABLE for pciide1:0, but it's only logged once and 
everything seems to still work fine.  Here's the section of the 
1.6.1_STABLE dmesg:

fdc0 at isa0 port 0x3f0-0x3f7 irq 6 drq 2
fd0 at fdc0 drive 0: 1.44MB, 80 cyl, 2 head, 18 sec
isapnp0: no ISA Plug 'n Play devices found
biomask ef65 netmask ef65 ttymask ffe7
pciide1:0: bogus intr
Kernelized RAIDframe activated


I tried Manuel's patch to pdcide.c, but it didn't fix the problem, 
perhaps a similar patch is needed for SiS?  Sorry, I don't completely 
understand the pdcide changes so I haven't touched any other *ide source.

I entered ddb with ctrl-alt-esc and did what Manuel suggested in an 
earlier e-mail...

>When the kernel loops on intr, can you try to enter ddb, and get a
>stack trace for the atabus* threads ?
>ps will give you the PID of the threads, you can get the trace via
>trace/t 0t<pid>

ps yields the following output:

PID   PPID   PGRP   UID   S   FLAGS   LWPS   COMMAND   WAIT
9   0   0   0   2   0x20200   1   pms0  
8   0   0   0   2   0x20200   1   atabus3
 >7   0   0   0   2   0x20200   1   atabus2
6   0   0   0   2   0x20200   1   atabus1   atarst
5   0   0   0   2   0x20200   1   atabus0   atarst
4   0   0   0   2   0x20200   1   usb1   usbdly
3   0   0   0   2   0x20200   1   usbtask   usbtsk
2   0   0   0   2   0x20200   1   usb0   usbdly
1   0   0   0   2       0       1   init   initexe
0   -1   0   0   2   0x20200   1   swapper   cfpend


trace/t 0t7 yields the following output:

trace: pid 7 at 0x0
uvm_fault(0xc0745aa0, 0, 0, 1) -> 0xe
kernel: page fault trap, code=0
Faulted in DDB; continuing...

trace/t 0t6 yields the following output:

trace: pid 6 at 0xcfc61d2c
ltsleep(cfc61d9c,10,c0664249,1,0) at netbsd:ltsleep+0x317
__wdcwait_reset(c0baca34,3,0,0,0) at netbsd:__wdcwait_reset+0x2bf
__wdcprobe(c0baca34,0,0,0,0) at netbsd:_wdcprobe+0x332
atabusconfiig(c0ba8b00,0,0,cfc4d2a8,cfc44820) at netbsd:atabusconfig+0x4d
atabus_thread(c0ba8b00,800000,809000,0,c010030c) ata 
netbsd:atabus_thread+0x52

trace/t 0t5 yields the following output:
same as pid 6, but at 0xcfc5dd2c




I've got the following hardware (taken from dmesg after booting a "good" 
kernel):
Basically, a QUANTUM FIREBALL HD, a Maxtor HD, and a Sony CD-RW on the 
SiS controller; and a QUANTUM FIREBALL HD, a Maxtor HD on the Promise 
controller.

pciide0 at pci0 dev 2 function 5: Silicon Integrated System 735 IDE 
controller (rev. 0xd0)
pciide0: bus-master DMA support present
pciide0: primary channel wired to compatibility mode
wd0 at pciide0 channel 0 drive 0: <QUANTUM FIREBALLlct08 08>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 8063 MB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 16514064 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 4 (Ultra/66)
pciide0: primary channel interrupting at irq 14
wd0(pciide0:0:0): using PIO mode 4, Ultra-DMA mode 4 (Ultra/66) (using 
DMA data transfers)
pciide0: secondary channel wired to compatibility mode
atapibus0 at pciide0 channel 1: 2 targets
cd0 at atapibus0 drive 0: <SONY    CD-RW  CRX175A1, , 5YS2> type 5 cdrom 
removable
cd0: 32-bit data port
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2 (Ultra/33)
wd1 at pciide0 channel 1 drive 1: <Maxtor 6Y080P0>
wd1: drive supports 16-sector PIO transfers, LBA addressing
wd1: 78167 MB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 160086528 
sectors
wd1: 32-bit data port
wd1: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
pciide0: secondary channel interrupting at irq 15
cd0(pciide0:1:0): using PIO mode 4, Ultra-DMA mode 2 (Ultra/33) (using 
DMA data transfers)
wd1(pciide0:1:1): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using 
DMA data transfers)
pciide1 at pci0 dev 9 function 0: Promise Ultra100/ATA Bus Master IDE 
Accelerator (rev. 0x02)
pciide1: bus-master DMA support present
pciide1: primary channel configured to native-PCI mode
pciide1: using irq 5 for native-PCI interrupt
wd2 at pciide1 channel 0 drive 0: <QUANTUM FIREBALLlct08 08>
wd2: drive supports 16-sector PIO transfers, LBA addressing
wd2: 8063 MB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 16514064 sectors
wd2: 32-bit data port
wd2: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 4 (Ultra/66)
wd2(pciide1:0:0): using PIO mode 4, Ultra-DMA mode 4 (Ultra/66) (using 
DMA data transfers)
pciide1: secondary channel configured to native-PCI mode
wd3 at pciide1 channel 1 drive 0: <Maxtor 6Y080P0>
wd3: drive supports 16-sector PIO transfers, LBA addressing
wd3: 78167 MB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 160086528 
sectors
wd3: 32-bit data port
wd3: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
wd3(pciide1:1:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using 
DMA data transfers)


Thanks,
Michael.




Manuel Bouyer wrote:

>On Fri, Oct 17, 2003 at 12:27:34PM +0900, NISHIO Yasuhiro wrote:
>  
>
>>>I just tried on my promise U100, I get them too. My U66 or U133 don't have
>>>this problem, it seems to be a quirk or the U100.
>>>      
>>>
>>uum, I'll try to use another IDE card at this week-end if I can get it.
>>    
>>
>
>Hi,
>can you try the attached patch on your U100 ? This solves the "bogus intr"
>messages for me
>
>  
>
>------------------------------------------------------------------------
>
>Index: pdcide.c
>===================================================================
>RCS file: /cvsroot/src/sys/dev/pci/pdcide.c,v
>retrieving revision 1.2
>diff -u -r1.2 pdcide.c
>--- pdcide.c	2003/10/11 17:40:15	1.2
>+++ pdcide.c	2003/10/19 14:30:27
>@@ -280,6 +280,8 @@
> 		}
> 		mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */
> 		mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */
>+		if (PDC_IS_265(sc))
>+			mode |= 0x80001100; /* from BIOS */
> 		WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR  0x%x, "
> 		    "now 0x%x\n",
> 		    bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh,
>@@ -295,12 +297,12 @@
> 		WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode),
> 		    DEBUG_PROBE);
> 		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM,
>-		    mode | 0x1);
>+		    mode & ~0x1);
> 		mode =
> 		    bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM);
> 		WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE);
> 		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM,
>-		    mode | 0x1);
>+		    mode & ~0x1);
> 	}
> 
> 	for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
>@@ -316,6 +318,9 @@
> 		}
> 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
> 		    PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr);
>+		/* clear interrupt, in case there is one pending */
>+		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
>+		    IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, IDEDMA_CTL_INTR);
> 	}
> 	if (!PDC_IS_268(sc)) {
> 		WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state "
>@@ -510,10 +515,11 @@
> 			continue;
> 		if (scr & PDC2xx_SCR_INT(i)) {
> 			crv = wdcintr(wdc_cp);
>-			if (crv == 0)
>+			if (crv == 0) {
> 				printf("%s:%d: bogus intr (reg 0x%x)\n",
> 				    sc->sc_wdcdev.sc_dev.dv_xname, i, scr);
>-			else
>+				pciide_irqack(wdc_cp);
>+			} else
> 				rv = 1;
> 		}
> 	}
>  
>