Subject: Hyperthreading Guidance
To: None <>
From: John R. Shannon <>
List: current-users
Date: 10/28/2003 12:34:25
Hash: SHA1

Am I better off enabling or disabling hyperthtreading on a twin Xeon system?

With it enabled, dmesg shows:

cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel Pentium 4 (686-class), 2799.29 MHz, id 0xf25
cpu0: features bfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features bfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX>
cpu0: features bfebfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF>
cpu0: I-cache 12K uOp cache 8-way, D-cache 8 KB 64b/line 4-way
cpu0: L2 cache 512 KB 64b/line 8-way
cpu0: ITLB 4K/4M: 64 entries
cpu0: DTLB 4K/4M: 64 entries
cpu0: calibrating local timer
cpu0: apic clock running at 133 MHz
cpu0: 16 page colors
cpu1 at mainbus0: apid 6 (application processor)
cpu1: starting
cpu1: Intel Pentium 4 (686-class), 2799.23 MHz, id 0xf25
cpu1: features bfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu1: features bfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX>
cpu1: features bfebfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF>
cpu1: I-cache 12K uOp cache 8-way, D-cache 8 KB 64b/line 4-way
cpu1: L2 cache 512 KB 64b/line 8-way
cpu1: ITLB 4K/4M: 64 entries
cpu1: DTLB 4K/4M: 64 entries
cpu2 at mainbus0: apid 1 (application processor)
cpu2: starting
cpu2: Intel Pentium 4 (686-class), 2799.22 MHz, id 0xf25
cpu2: features bfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu2: features bfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX>
cpu2: features bfebfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF>
cpu2: I-cache 12K uOp cache 8-way, D-cache 8 KB 64b/line 4-way
cpu2: L2 cache 512 KB 64b/line 8-way
cpu2: ITLB 4K/4M: 64 entries
cpu2: DTLB 4K/4M: 64 entries
cpu3 at mainbus0: apid 7 (application processor)
cpu3: starting
cpu3: Intel Pentium 4 (686-class), 2799.21 MHz, id 0xf25
cpu3: features bfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu3: features bfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX>
cpu3: features bfebfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF>
cpu3: I-cache 12K uOp cache 8-way, D-cache 8 KB 64b/line 4-way
cpu3: L2 cache 512 KB 64b/line 8-way
cpu3: ITLB 4K/4M: 64 entries
cpu3: DTLB 4K/4M: 64 entries

The two "logical" CPUs are treated by the scheduler as ordinary processors?

=2D --=20

John R. Shannon
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