In Message <20031012171415.GB391@antioche.eu.org> ,
   Manuel Bouyer <bouyer@antioche.eu.org> wrote:

=>[ Sorry for the delay, I've been busy last 2 weeks ]
=>
=>On Sat, Sep 27, 2003 at 12:43:14PM -0400, Gary Duzan wrote:
=>> [...]
=>> wd0(pciide0:0:0): using PIO mode 4, Ultra-DMA mode 4 (Ultra/66) (using DMA data transfers)
=>> pciide0:1: before reset, st0=0x50, st1=0x50
=>> pciide0:1:0: after reset, sc=0x1 sn=0x1 cl=0x14 ch=0xeb
=>> pciide0:1:1: after reset, sc=0x7f sn=0x7f cl=0x7f ch=0x7f
=>> pciide0:1: wdcwait_reset() end, st0=0x0 er0=0x1, st1=0x7f er1=0x7f
=>
=>This is the problem, reading any register from the slave return 0x7f.
=>This shouldn't happen, the master may be misbehaving.
=>It worked before though, so maybe there's a workaround possible.
=>
=>Can you send the debug output of a previous working kernel ?
=>I'd like to see what was returned with the old probe.

   Ok, I managed to PXEboot a 1.6.1_STABLE(today) on this box, and
here are the relevant bits:

===========================================================================
pciide0 at pci0 dev 9 function 0: Nvidia Corporation product 0x0065 (rev. 0xa2)
pciide0: bus-master DMA support present, but unused (no driver support)
pciide0: primary channel configured to compatibility mode
pciide0:0: before reset, st0=0x50, st1=0x0
pciide0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0: wdcwait_reset() end, st0=0x50, st1=0x0
pciide0:0: after reset, ret_value=0x3
pciide0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0: before reset, st0=0xff, st1=0xff
pciide0: primary channel interrupting at irq 14
pciide0:0: before reset, st0=0x50, st1=0x0
pciide0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0: wdcwait_reset() end, st0=0x50, st1=0x0
pciide0:0: after reset, ret_value=0x3
pciide0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
wdcwait: timeout (time=30001), status 0 error 0 (mask 0x48 bits 0x40)
wdc_ata_get_parms: wdc_c.flags=0x131
wdcwait: timeout (time=30001), status 0 error 0 (mask 0x48 bits 0x40)
wdc_ata_get_parms: wdc_c.flags=0x131
pciide0:0:1: IDENTIFY failed (1)
wdcattach: ch_drive_flags 0x1 0x0
wd0 at pciide0 channel 0 drive 0: <ST320423A>
wd0: drive supports 32-sector PIO transfers, LBA addressing
wd0: 19536 MB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 40011300 sectors
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 4 (Ultra/66)
pciide0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
pciide0:0: wdcwait_reset() end, st0=0x50, st1=0x0
pciide0: secondary channel configured to compatibility mode
pciide0:1: before reset, st0=0x50, st1=0x50
pciide0:1:0: after reset, sc=0x1 sn=0x1 cl=0x14 ch=0xeb
pciide0:1:1: after reset, sc=0x7f sn=0x7f cl=0x7f ch=0x7f
pciide0:1: wdcwait_reset() end, st0=0x0, st1=0x7f
pciide0:1: after reset, ret_value=0x3
pciide0:1:0: after reset, sc=0x1 sn=0x1 cl=0x14 ch=0xeb
pciide0:1:1: after reset, sc=0x7f sn=0x7f cl=0x7f ch=0x7f
pciide0:1: before reset, st0=0xff, st1=0xff
pciide0: secondary channel interrupting at irq 15
pciide0:1: before reset, st0=0x0, st1=0x7f
pciide0:1:0: after reset, sc=0x1 sn=0x1 cl=0x14 ch=0xeb
pciide0:1:1: after reset, sc=0x7f sn=0x7f cl=0x7f ch=0x7f
pciide0:1: wdcwait_reset() end, st0=0x0, st1=0x7f
pciide0:1: after reset, ret_value=0x3
pciide0:1:0: after reset, sc=0x1 sn=0x1 cl=0x14 ch=0xeb
pciide0:1:1: after reset, sc=0x7f sn=0x7f cl=0x7f ch=0x7f
wdcattach: ch_drive_flags 0x2 0x1
atapibus0 at pciide0 channel 1: 2 targets
cd0 at atapibus0 drive 0: <SONY CD-ROM CDU4821, MT1198-B Firmware, S0.Q> type 5 cdrom removable
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2 (Ultra/33)
wd1 at pciide0 channel 1 drive 1: <MAXTOR 6L080L4>
wd1: drive supports 16-sector PIO transfers, LBA addressing
wd1: 76345 MB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 156355584 sectors
wd1: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
pciide0:1:0: after reset, sc=0x1 sn=0x1 cl=0x14 ch=0xeb
pciide0:1:1: after reset, sc=0x7f sn=0x7f cl=0x7f ch=0x7f
pciide0:1: wdcwait_reset() end, st0=0x0, st1=0x7f
===========================================================================

   Of course, is seems the 1.6 branch hasn't learned about NVidia IDE
controllers yet, so this is without DMA, but maybe it will be of use.
If you need a version from the trunk, I'll try grabbing a kernel from
about a month ago and see how it does.

   Also of note, I tried running just wd1 as the master, and that
worked, as did wd1 as the master with cd0 as the slave. It is only
the cd0 master/wd1 slave case that doesn't work under current. I
suspect from the numbers above that this is going to end up being
a case of "don't do that", which is fine with me.

					Gary Duzan