More info:

The parallel ATA card (with pciide debugging on) shows:

    Base address register at 0x10
      type: 32-bit i/o
      base: 0x0000a400, size: 0x00000008
    Base address register at 0x14
      type: 32-bit i/o
      base: 0x0000a800, size: 0x00000004
    Base address register at 0x18
      type: 32-bit i/o
      base: 0x0000ac00, size: 0x00000008
    Base address register at 0x1c
      type: 32-bit i/o
      base: 0x0000b000, size: 0x00000004
    Base address register at 0x20
      type: 32-bit i/o
      base: 0x0000b400, size: 0x00000010
    Base address register at 0x24
      type: 32-bit nonprefetchable memory
      base: 0xef120000, size: 0x00004000


The TX4 serial ATA card shows:

    Base address register at 0x10
      type: 32-bit i/o
      base: 0x0000b800, size: 0x00000040
    Base address register at 0x14
      type: 32-bit i/o
      base: 0x0000bc00, size: 0x00000010
    Base address register at 0x18
      type: 32-bit i/o
      base: 0x0000c000, size: 0x00000080
    Base address register at 0x1c
      type: 32-bit nonprefetchable memory
      base: 0xef124000, size: 0x00001000
    Base address register at 0x20
      type: 32-bit nonprefetchable memory
      base: 0xef100000, size: 0x00020000
    Base address register at 0x24
      not implemented(?)