Subject: Re: wi0 timeouts
To: None <email@example.com>
From: Andrew Cagney <firstname.lastname@example.org>
Date: 12/05/2002 18:44:30
> 1 Let's call the interrupt enable register IER and the event status
> register ESR. I was assured once by an engineer at Agere that it
> was the level of bits in (IER & ESR) which triggered interrupts, not
> the transition of the bits. So I removed the code which disabled and
> re-enabled all interrupts at the top and bottom of wi_intr, respectively,
> because it looked to me like a superfluous protection against NetBSD
> re-entering wi_intr. Because the change did not do me any harm, I
> left it, but maybe it is the wrong thing. Try zeroing WI_INT_EN at the
> top of wi_intr, and writing WI_INTRS before getting out. Tell me what
> you observe.
1-6 release appears to still contain that code. I'm seeing wi0 problems
using that official kernel.