On Sat, 12 Oct 2002 02:12 am, you wrote:
> Gary Thorpe <gathorpe79@yahoo.com> writes:
> > Shouldn't the most important factor be the bus speed, since all newer
> > x86 cpus have an internal clock which differs from the bus clock? Sin=
ce
> > SMP does communication at bus clock speeds, why should differences in
> > the internal clock speed matter? Although different varieties may not
> > interoperate properly, why should running using a 800Mhz PIII and a
> > 700Mhz PIII be problematic if both use identical bus specifications
> > (these two in particular may not have identical bus specifications, b=
ut
> > the question is regarding the case that two cpus have diffeent intern=
al
> > speeds but have the same bus specifications)?
>
> Two devices running at different speeds should be assumed to be
> different revisions of the silicon and therefore potentially speak
> subtly different versions of the bus protocol, unless you have very
> good information otherwise.

My understanding was that for a model of processor, a speed rating is rea=
lly a=20
quality control aspect of the manufacturing process. There may be several=
=20
chips that make it through the maufacturing process, but they reliably ru=
n up=20
to different speeds due to small variations in manufacturing process. The=
=20
manufacturer then releases these with different speed ratings. Note they =
are=20
all the same electrical design. This information relates to processors ar=
ound=20
a couple of years ago. It may be different now.

Anyways, I now have both CPUs running at the same speed (that of the slow=
er=20
cpu) and have slowed down my memory in the process. I suspect a registere=
d /=20
unregistered set of DDR memory issue,  investigating.....

> > If it really won't work, anyone know why not?
>
> Almost all of this is not "really won't work" but "not guaranteed to
> work, if it breaks you get to keep both pieces".

=2E..like overclocking.


Murray