--- Murray Armfield <murray.armfield@arconsulting.com.au> wrote:
> On Sat, 12 Oct 2002 02:12 am, you wrote:
> > Gary Thorpe <gathorpe79@yahoo.com> writes:
> > > Shouldn't the most important factor be the bus speed, since all
> newer
> > > x86 cpus have an internal clock which differs from the bus clock?
> Since
> > > SMP does communication at bus clock speeds, why should
> differences in
> > > the internal clock speed matter? Although different varieties may
> not
> > > interoperate properly, why should running using a 800Mhz PIII and
> a
> > > 700Mhz PIII be problematic if both use identical bus
> specifications
> > > (these two in particular may not have identical bus
> specifications, but
> > > the question is regarding the case that two cpus have diffeent
> internal
> > > speeds but have the same bus specifications)?
> >
> > Two devices running at different speeds should be assumed to be
> > different revisions of the silicon and therefore potentially speak
> > subtly different versions of the bus protocol, unless you have very
> > good information otherwise.
> 
> My understanding was that for a model of processor, a speed rating is
> really a 
> quality control aspect of the manufacturing process. There may be
> several 
> chips that make it through the maufacturing process, but they
> reliably run up 
> to different speeds due to small variations in manufacturing process.
> The 
> manufacturer then releases these with different speed ratings. Note
> they are 
> all the same electrical design. This information relates to
> processors around 
> a couple of years ago. It may be different now.

No its the same. They use the same core and you will generally be able
to find solid information on bus differences. Not all PIIIs will be
identical, but for a particular speed range, they will be the same
except for the core clock speed.

> Anyways, I now have both CPUs running at the same speed (that of the
> slower 
> cpu) and have slowed down my memory in the process. I suspect a
> registered / 
> unregistered set of DDR memory issue,  investigating.....
> 
> > > If it really won't work, anyone know why not?
> >
> > Almost all of this is not "really won't work" but "not guaranteed
> to
> > work, if it breaks you get to keep both pieces".
> 
> ...like overclocking.
> 
> 
> Murray

Overclocking is running a cpu beyond its specified rating. CPUs with
different core speeds can still meet the same specification for SMP
compatibility. It may not be ideal, buts thats another question.

For Intel cpus, it is not impossible and is in fact quite likely, given
that a PIII at 700MHZ is very likely to be identical to a PIII at
800MHZ (except for its core clock speed). Given this, they should work
in an SMP configuration. Note: Celerons are not intended for SMP
configurations but people are still using them (because they follow the
same cache coherancy protocols and bus protocols). Again, the same
silicon is used in their cores.

If they couldn't be used outright, then slowing the core clock speed of
one to match the other would not help, because the protocols would
still be incompatible.

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