Subject: Re: Wierd time-keeping with i386 MP kernel
To: None <paul@whooppee.com>
From: Martin Husemann <martin@duskware.de>
List: current-users
Date: 02/03/2002 13:08:55
I can not reproduce this with a MP branch kernel from sources as of
January 31:

     remote           local      st poll reach  delay   offset    disp
=======================================================================
*nightfall.duskw 192.168.150.92   2   64  377 0.00134  0.001354 0.00096

This is the CPU related part of the dmesg:

mainbus0: Intel MP Specification (Version 1.4) (OEM00000 PROD00000000)
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel Pentium II/Celeron (Deschutes) (686-class), 400.94 MHz
cpu0: features 183fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features 183fbff<PGE,MCA,CMOV,FGPAT,PSE36,MMX,FXSR>
cpu0: I-cache 16 KB 32b/line 4-way, D-cache 16 KB 32b/line 4-way
cpu0: L2 cache 512 KB 32b/line 4-way
cpu0: ITLB 32 4 KB entries 4-way, 2 4 MB entries fully associative
cpu0: DTLB 64 4 KB entries 4-way, 8 4 MB entries 4-way
cpu0: calibrating local timer
cpu0: apic clock running at 100 MHz
cpu0: 32 page colors
cpu1 at mainbus0: apid 1 (application processor)
cpu1: starting
cpu1: Intel Pentium II/Celeron (Deschutes) (686-class), 400.91 MHz
cpu1: features 183fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu1: features 183fbff<PGE,MCA,CMOV,FGPAT,PSE36,MMX,FXSR>
cpu1: I-cache 16 KB 32b/line 4-way, D-cache 16 KB 32b/line 4-way
cpu1: L2 cache 512 KB 32b/line 4-way
cpu1: ITLB 32 4 KB entries 4-way, 2 4 MB entries fully associative
cpu1: DTLB 64 4 KB entries 4-way, 8 4 MB entries 4-way

Martin