On Thu, Oct 28, 1999 at 03:23:30AM -0400, Charles M. Hannum wrote:
> > Try to find one that uses one of the multi-port 16650 chips.  They have
> > up to 64 bytes of FIFO per channel and RTS/CTS flow control in hardware;
> > this takes a *lot* of load off the CPU by reducing the number of interrupts
> > generated, and also eliminates the possibility of dropped characters.
> 
> Technically, they do not `reduc[e] the number of interrupts', unless
> you increase the FIFO threshold for generating an interrupt.  But
> doing so in turn limits the possible RTS/CTS threshold, and thus you
> don't necessarily get any better protection against FIFO overflows.

ST16C65X can control the RTS output automatically.  WHen first FIFO treshold
is reached, the chip generates an interrupt to the CPU.  If the CPU does not
read the data off the FIFO and the second treshold is reached, the chip
negates RTS.  After this, there's _still_ some room in the FIFO to receive
characters that may be sent by hosts that don't immediately react to CTS input
changes.

> Optimizing the combination of interrupt threshold and RTS/CTS
> threshold is complicated (and by nature is dynamic, since it's
> affected by other interrupt load), and the driver does not currently
> attempt to do this.  (Nobody else's does either, AFAIK.)

Why bother when the hardware can do if for you :-)

  -jm