Sean Doran wrote:
> The assembly code egcs emits from cc -S (with or without -O/-O2/-O3) seems
> sane - it boils down to:
> 
> .L8:
>         movl %esi,%ebx
>         sall %cl,%ebx
>         jmp .L7
>         .align 4
> .L9:
>         movl %esi,%ebx
>         sarl %cl,%ebx
> 
> So the 386 is doing something "interesting".
> 
> ./shift r 0x7fffffff 34
> shr 0x7fffffff, 0x22 -> 0x1fffffff

for IA32 ;-) we mask off the lower 5 bits of the shift count and shift by
this much (so i guess it's mod 32, more or less).  it also means that
specifying a shift count of 32 will not shift the number at all.  this is
apparently allowed by the C spec.  oh well...

thanks for all the responses.

later.


-- 
Colin Wood                                 cwood@ichips.intel.com
Component Design Engineer - PMD                 Intel Corporation
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I speak only on my own behalf, not for my employer.