According to Brian C. Grayson:
>
>  Maybe I'm wrong, but don't all Modern Processors (PPC 604e,
>Pentium, PPro, PII, UltraSparc, R10000, etc.) and/or their bus
>controllers support cache coherence automatically in hardware? 
>If so, any extra work (over a uniproc config) for maintaining
>coherence would only occur when two processors are _modifying_
>the _same_ memory location, modulo cache line size (or one
>writing and the other reading).
>

For people who want to find out about MP Intel style there is a
document on the intel web page that describes the MP support for the
PPro & PII processors.  I don't know where it is exactly on their
pages but I do recall it being in a fairly logical place.  Failing
that, I have a copy of the pdf (390852 bytes).

-- 
Brett Lymn, Computer Systems Administrator, British Aerospace Australia
===============================================================================
  And the monks would cry unto them, "Keep the bloody noise down!"
  - Mort, Terry Pratchett.