On Sun, 30 Aug 1998, Brian C. Grayson wrote:

>   Maybe I'm wrong, but don't all Modern Processors (PPC 604e,
> Pentium, PPro, PII, UltraSparc, R10000, etc.) and/or their bus
> controllers support cache coherence automatically in hardware? 
> If so, any extra work (over a uniproc config) for maintaining
> coherence would only occur when two processors are _modifying_
> the _same_ memory location, modulo cache line size (or one
> writing and the other reading).

One processor that does not is the StrongARM (arm32 port) This has a
virtually address cache and no cache snooping. I would call this fairly
modern as the StrongARM family is still being developed. It may be
considered though that the overhead of keeping things coherence is just
too much.

Cheers,
				Mark