Subject: Re: SMP/flogging a dead horse
To: Erik E. Fair <email@example.com>
From: Brian C. Grayson <firstname.lastname@example.org>
Date: 08/30/1998 01:10:56
On Sat, Aug 29, 1998 at 10:00:12AM -0700, Erik E. Fair wrote:
> The issue is that when you have more than one processor, each with
> its own cache(s), you have to keep them consistent with each other
> and with main RAM, that is, "coherent."
> If you spend too much time flushing out the caches to main RAM to
> keep consistency, you lose performance.
Maybe I'm wrong, but don't all Modern Processors (PPC 604e,
Pentium, PPro, PII, UltraSparc, R10000, etc.) and/or their bus
controllers support cache coherence automatically in hardware?
If so, any extra work (over a uniproc config) for maintaining
coherence would only occur when two processors are _modifying_
the _same_ memory location, modulo cache line size (or one
writing and the other reading).
This would only occur in a multithreaded kernel, or a
multithreaded or SYSVSHM app, and not in everyday traditional
single-thread Unix workload stuff like gcc, sh, awk. And a
well-written _multithreaded_ app is written/optimized to
minimize coherence traffic, among other things. :)
Lou B: "What do you call a fly that has lost its wings? A walk."
Rick: (pause)..."I don't get it."