Date:	Sat, 29 Aug 1998 12:32:16 -0400
	From:	nm <nmanisca@vt.edu>
	Subject: Re: SMP/flogging a dead horse 

	Does having an onchip L2 (like the ppro) make the cache hit less
	of an issue than on say a pentium chip?

The issue is that when you have more than one processor, each with
its own cache(s), you have to keep them consistent with each other
and with main RAM, that is, "coherent." If the caches end up with
different ideas of what a particular piece of main RAM contains,
you're dead, unless you have some way to tell which one is wrong.

If you spend too much time flushing out the caches to main RAM to
keep consistency, you lose performance (the caches are there because
they are faster than main RAM, and are supposed to keep the stuff
a program is working on at the time - if you don't hit them, you
run no faster than main RAM, which is far too slow). If you don't
flush them often enough to achieve coherency, you get inconsistent
data, which means the computer will give you wrong answers. Evil.

Doing any MP or SMP configuration is tricky when you've got caches
to contend with (but almost every modern processor has an L1, and
often an L2, cache).

Go read that book I recommended. Really. It discusses these issues
in some depth without getting too grotty.

	Erik E. Fair	fair@clock.org