Subject: Re: VIA VP2 chipset
To: Dave Rand <email@example.com>
From: Ted Lemon <firstname.lastname@example.org>
Date: 02/04/1998 22:25:48
> The cause? The cache memory had failed. Small amounts of high-speed
> cache cannot (generally) be error checked or error corrected without
> the addition of some serious time penalties. Would you trade a 2x to 4x
> performance decrease for a more reliable system? This is the real cost.
Bit failures in system cache memory are quite easily and rapidly
detected, as your example suggests. The same cannot be said for bit
errors in main memory, unless they happen to fall on pages in which
vital kernel data structures or code happen to live.