Subject: Re: silo overflows, was fifo overruns
To: David Jones <email@example.com>
From: Jonathan Stone <jonathan@DSG.Stanford.EDU>
Date: 11/11/1997 18:31:38
>From: David Jones <firstname.lastname@example.org>
>Date: Tue, 11 Nov 1997 18:22:56 -0500 (EST)
>Sparc IPC (25 MHz sun4c, zs8530, supposedly 16-character FIFO)
>- Drops characters at 19200.
>The problem is the 8530: it is a very slow part; it must be accessed at
>most once every 2us.
Sorry, that turns out not to be the case. This is a problem, and
handling it with software delays in interrupt handlers is ugly.
That's why more modern motherboards provide hardware support to
prevent acess to the SCC data registers more than once every 2ms.
Turbochannel Alphas provide such support.
However, even without that hardware fix, DECstations can keep up with
an 8530 at 57.6 kbps. In fact, a 40MHz DECstation could keep up with
115.2kbps, if only the silly SCC chip could go that fast without
I'd tend to conclude this is a problem with the NetBSD Sparc kernel
interrupt handling, or the zs driver, or both.
(It's curious that the NTP clock drift between sparcs and Decstations
seems comparable to the limits on SCC speed. Perhaps they have the
same underlying cause....)