Jason Thorpe <thorpej@nas.nasa.gov> writes:
> Michael Richardson <mcr@sandelman.ottawa.on.ca> wrote:

> >   It usually results in a requirement to go through SMC's ridiculously
> > slow/large setup program to reset the ram base address.. I had a 3c509
> > around, so I substituted it instead. Next boot had my 509 and my ast
> > four port clone at the same irq.

>Well, strictly speaking, this Works.  I.e. I'm assuming that the
>3c509 and the AST both are working...

I don't think it works.  While you can set the interrupt controller on
PCs for edge or level trigger you can't do that with the UARTs.  The
UARTs assert the IRQ line when an interrupt condition occurs and you
have to clear that condition manually from the driver.  Any interrupt
that comes in before the clearing (as from a 3C509 but also from the
UART itself (see AN-491 from NatSemi where this is discussed at
length) is lost as it can't raise an edge.

>Both the ast and ep use EDGE triggered interrupts, thus the line
>can be shared.

No, the they don't.  PCs UARTs only generate level triggered
interrupts.  That the interrupt controller is set up for edge
triggered interrupts doesn't make the situation any better.

-- 
Christoph Badura	bad@flatlin.ka.sub.org

You don't need to quote my .signature.  Everyone has seen it by now.
Besides, it doesn't add anything to the current thread.