Subject: PCI I/O address mask/size change?
To: None <mycroft@NetBSD.ORG>
From: Chris G Demetriou <Chris_G_Demetriou@ux2.sp.cs.cmu.edu>
Date: 08/05/1996 00:36:14
[ delay due to vacation... ]
> Fri Jul 26 02:35:37 EDT 1996
> Update of /a/cvsroot/src/sys/dev/pci
> In directory pain.lcs.mit.edu:/a/tmp/cvs-serv10686
> Modified Files:
> Log Message:
> Changes PCI_MAPREG_IO_ADDR_MASK to 0xfffe.
What is the reason for this change?
Previously, the value was:
#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe
To quote the PCI Local Bus Specification (Revision 2.0), page 160:
"Base registers that map into I/O space are always 32 bits with bit 0
hardwired to a 1, bit 1 is reserved and must return 0 on reads, and
the other bits are used to map the device into I/O space (see Figure
6-6)." [ the ... interesting use of parallelism is theirs -- cgd ]
Earlier in the spec, it says that devices must decode all 32 address
Unless you have information that supersedes the 2.0 spec, the original
definition was correct and the new one is not.
Just because the i386 can't use them doesn't mean that other ports
can't (and that their firmware doesn't)...
Since in the rest of my mail i've not noticed any rationale for that
change and no rationale was given in the source code, if i don't hear
something "soon" (i.e. in the next few days) which confirms that the
change was correct according to a PCI spec, i'm going to back it out.