>There is no such thing.  Memory accesses require exactly the same
>amount of time whether there is RAM there or not.  If there is nothing
>there, they simply return some random digital representation of the
>electrical signals floating around the bus when the memory access is
>attempted.  Thus, this couldn't cause a bus error.

No, I take Ken's point. I was once involved in m68k development.
There I had a watchdog on the _asynchronous_ bus. If it saw an
address strobe it started. If no DTACK was forthcomming it hit BERR.
This trapped back into the kernel to say that someone had done
something stupid.

I don't think, however, that this would be a problem in this case as
we should _only_ have real memory mapped into the page directory.

As for one of the comments (from derMouse, I think) this bit of code
in Spice is a _complete, total, utter HACK_ and I have given up on
it. (It's trying to find out the extent of the data segment and the
current limit) I'm rewriting it to use system calls where possible
to find the information.

BUT The code does work if I change all occurences of SIGSEGV to
SIGBUS. Hence why i asked as to what they mean and why NetBSD is
different to historic BSD?

Alex.

BTW If anyone wants a copy of the code or diffs then drop me a line.
My simulations seem "sensible" but I haven't built any of the
resulting circuits yet ;-)