I am writing a driver for a satellite receiver.

I have some questions on the timing, I'll lay out my
current understanding please correct me where I'm wrong!

The satellite receiver board has two frame buffer and while it is
in normal receive mode, the satellite will be receiving data into
one buffer while the computer endeavors to empty out the other buffer.
I'm assuming that when data being written to the satellite buffer
that this will not affect the timing of reads from the CPU buffer.

According to the specifications I will be receiving a 7000 byte frame
of data every 36 milliseconds. 

The receiver board itself is a 16 bit ISA bus card.  The ISA bus
operates at 6-8 Mhz (I'll use 6 to be conservative)

Given that the 6Mhz, a bus cycle is .166us.

Read requests to the memory require 4/5 cycle (?)
so the time to read each word will be about .8us

The satellite board can transfer 16 bits words so I will need to
do about 3500 16 bit transfers to empty the buffer.

The total read time is is going to be 3500*.8us =  2.8ms

What is the relationship between motherboard clock cycles
(486 dx2/66) and ISA bus cycles? Is the total transfer time
for a memory to memory move fromm emory on the ISA bus to
memory on the motherboard 4 cycles at 33Mhz + 4 cycles at 6 Mhz
or are they overlapped somehow??

The disk controller is a VLB controller, if there are DMA tranfers
to the disk in progress will this slow the transfers from the ISA
bus?

Let's assume a total memory to memory transfer time of 5ms/frame
and that frames are arriving every 36ms, is this a reasonable rate
for a PC to handle? If not what is a good upper boundry.

Are other drivers going to get upset that one ISR is taking so much time?

Larry