Since I am one of the many i386 owners afflicted with caches that don't snoop
DMA cycles, thus requiring me to run without the external cache, I decided to
look through the sources to see what kinds of assumptions were made about
caches.  (I'm asking current-users rather than port-i386 since cache consistency
is a question affecting any reasonable computer.  Of course, the architecture-
independant answer is probably "Hey, the hardware is supposed to just *work*",
in which case the question becomes toy-computer specific...  :-)

I don't seem to see any kind of general facility for preparing a page for DMA
(e.g. flush the page out of hardware cache, or any other kinds of preparation
that might need to be done).  Have I just missed it, or does the software
make no preparations for starting a transfer other than just ticking the
device itself?  If not, is there an obvious place where to add code to warn
a deficient cache about an impending transfer?

Thanks, 
John Woods, jfw@funhouse.com