Subject: Re: CTIX architecture
To: Niklas Hallqvist <>
From: Per Fogelstrom <>
List: current-users
Date: 12/09/1994 10:35:43
> Well, there are ways to cheat, I think Appollo had a design with two
> 68000's one instruction out of sync with each other.  When the first
> trapped on an illegal memory access the MM hardware brought in the
> page and then the processors roles were switched so that the untrapped
> processor could continue the process.  Neat no?  The 68010 could
> restart instructions.  That was one of the reasons it existed.

Not exactly, the second CPU did the paging. When a "page fault" occured
the first processor was stalled, and the second was "started" to bring in
the correct page. It never trapped, because if it did you was lost since
it wasn't able to restart.

The 68010 did not restart instructions, it "continued". A somewhat hot
item discussed then, whether it was better to restart or continue.
One reason for "continue" was that it was "easy" to emulate non existing
hardware addresses.