Mark_Weaver@brown.edu writes:
> 
> Drew Hess <dhess@CS.Stanford.EDU> wrote:
> > Mark P. Gooderum writes:
> > > 
> > > But on clock speed versus memory speed, remember that a 486 still isn't
> > > any where close to a RISC chip in cycles per instruction ratio.
> > > 
> > 
> > 
> > Well, this is a topic for another place, but cycles/instruction is not 
> > necessarily a good benchmark for comparing architectures-- especially
> > when comparing load/store (e.g. "RISC") architectures to register/memory
> > (e.g. x86) architectures.
> 
> I think you missed the point.  The point is: a high cycles per
> instruction ratio means that having the internal clock be twice as
> fast as the external clock is likely to make a big difference in
> overall performance.
> 
> 


No, I think you missed the point of *my* post.  I took issue only with the
assertion that CPI has anything to do with the performance of the
i486 relative to a RISC machine.  

I wasn't commenting on the post as a whole, just on the comparison of i486 CPI 
vs. RISC CPI.  That's why I said "this is a topic for another place"; that is, 
because it wasn't relevant to NetBSD or the performance of variants of the 
i486.


-dwh-
dhess@cs.stanford.edu

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