Subject: Re: Cyberstorm (and Amiga cache)
To: None <amiga@NetBSD.ORG>
From: Jeffrey William Davis <firstname.lastname@example.org>
Date: 03/29/1996 10:47:34
> > At 40MHz, 1 clock = 25ns, which means a 'normal' bus cycle could take
> > no less time than 75ns! Hence, the 60ns DRAM keeps up at zero wait
> > states fine.
> At a 25 MHz bus clock, the access time must be well below 50 ns.
> If you take a look at any DRAM data book, you will notice that the DRAM
> access time means "access time from /RAS". For example, a 80 ns TC514410
> has "access time from /RAS" of 80 ns (hence the speed class '80 ns'), but
> a random read or write cycle time of 150 ns (minimum). This means that
> if the CPU wants to read any memory location _without_using_page_mode_
> or any similar system (which can't be used for random reads, anyway),
> the memory cycle will take 150 ns or more. With the CPU minimum memory
> cycle being 50, this is pretty slow. For a 70 ns chip the Toshiba memory
> data book lists the cycle time of 130 ns.
You seem to be a 'worst-case' kind of guy. :-) First of all, you are
starting your example with 80 and 70ns speeds. Second, you are not taking
advantage of the 'extra' time surrounding the actual memory cycle! Going
from the "what's the worst possible memory design" aspect, things aren't
going to add up. Have you ever designed a DRAM controller/interface???
Sometime when I have more time, I will put together some ASCII timing
diagrams of how all the pieces fit together. There are many areas where
you take advantage of timing overlaps with the bus address phase, allowing
DRAM cycles to 'complete' after the CPU bus cycle, and /CAS timing issues.
How and when data/address information is latched by the RAM board, and a
few dozen other issues (like memory layout for /RAS).
There is a good reason why they chose "access time from /RAS" to represent
the DRAM speed. I have learned that for simplicity, the ns rating of the
DRAM is quite representative of the performance you achieve, not the
'fastest performance' limit.
> > With 60ns DRAM, the access frequency works out to be 16.67MHz.
> Wrong, see above.
Not as wrong as you think.
Jeffrey W. Davis (317)451-0503 Domain: email@example.com
Software Engineer UUCP: deaes!c23jwd
Delco Electronics Corporation GM: 8-322-0503 Mail: CT40A
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