Subject: Re: Cyberstorm (and Amiga cache)
To: Jeffrey William Davis <email@example.com>
From: Jukka Marin <firstname.lastname@example.org>
Date: 03/29/1996 08:48:17
> First of all, your information is completely misleading. The 68040 requires
> three clocks for normal bus accesses.
Looking at the MC68040 USER'S MANUAL, page 8-9, I would say a "long-word
operand read" takes two clocks. In addition, the address outputs aren't
valid until after a short period _after_ the 2-clk period starts. All
signal buffering slows down the address outputs and limits the actual
memory access time even further.
> At 40MHz, 1 clock = 25ns, which means a 'normal' bus cycle could take
> no less time than 75ns! Hence, the 60ns DRAM keeps up at zero wait
> states fine.
At a 25 MHz bus clock, the access time must be well below 50 ns.
If you take a look at any DRAM data book, you will notice that the DRAM
access time means "access time from /RAS". For example, a 80 ns TC514410
has "access time from /RAS" of 80 ns (hence the speed class '80 ns'), but
a random read or write cycle time of 150 ns (minimum). This means that
if the CPU wants to read any memory location _without_using_page_mode_
or any similar system (which can't be used for random reads, anyway),
the memory cycle will take 150 ns or more. With the CPU minimum memory
cycle being 50, this is pretty slow. For a 70 ns chip the Toshiba memory
data book lists the cycle time of 130 ns.
When addressing DRAM, you also need to take the address multiplexer
delays into account. These with a small safety-margin may take another
20 ns, I assume.
> Can you find in the 68040 databook where it can do a 2-1-1-1 burst? I
> believe 3-2-2-2 is the limit.
Burst accesses must be 2-1-1-1 because the normal (burst inhibited) accesses
take 2 clocks.
> I will review my databooks and find the true capability of the MC040.
> Assuming a 2-1-1-1 burst, the maximum theoretical performance increase
> is 80%. A L2 cache is not going to achieve near this, and it is not
> going to be sustainable when moving data larger than the cache.
A cache could certainly do much better than the 130 ns of DRAM.
> With 60ns DRAM, the access frequency works out to be 16.67MHz.
Wrong, see above.
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