c23jwd@eng.delcoelect.com (Jeffrey William Davis) writes:

>at a finite speed!  Clocked at 40MHz, the DRAM subsystem is able to process
>all accesses immediately without any kind of delay (zero wait state).

At 40MHz the CPU can request a longword in 25ns, this requires at least
20ns DRAM. Do you still believe that the Warpengine has zero wait states ?
The fastest reasonable burst cycle is probably a 2-1-1-1 burst. At 40MHz
this yields a possible memory bandwidth of 128MByte/s but the WE memory
system just delivers about 50MByte/s.

>The reason L2 cache is so prevalent in the PC realm (and others) is due
>to the clock doubling, high CPU clock rates, and generally exceeding the
>DRAM technology of today.  For example, a 166MHz bus speed on a system
>with 3 clocks/access would require 18ns minimum speed RAM to run at full
>speed.

No CPU in a PC uses a 166MHz bus. The fastest Pentiums use 66MHz
on the bus and often have waitstates on L2 cache accesses.

Regards,
-- 
                                Michael van Elst

Internet: mlelstv@serpens.rhein.de
                                "A potential Snark may lurk in every tree."