On Mar 17, 12:20pm, "Markus Illenseer" wrote:
> mw wrote:
> > If some people with '40 and RZ3 could look into RZ3SetHWCloc(): at the
> > end of this function you'll find the following statements:
> >         *(acm + (ACM_CURSOR_POSITION+0)) = x & 0xff;
> >         *(acm + (ACM_CURSOR_POSITION+1)) = x >> 8;
> >         *(acm + (ACM_CURSOR_POSITION+2)) = y & 0xff;
> >         *(acm + (ACM_CURSOR_POSITION+3)) = y >> 8;
...
>  The other idea which comes to mind is that this register is probably
> 8Bit-only and the 040-interface in some machines will not access the
> register correctly.

  If that is the case, and since the registers appear to be sequential,
could the above code be modified to do a 16 bit write of the
byte-swapped values of x and y?  I.e:

	*((u_short *)(acm + (ACM_CURSOR_POSITION + 0))) =
	    ((x & 0xff) << 8) + ((x >> 8) & 0xff);
	*((u_short *)(acm + (ACM_CURSOR_POSITION + 2))) =
	    ((y & 0xff) << 8) + ((y >> 8) & 0xff);


Michael

-- 
Michael L. Hitch			INTERNET:  osymh@montana.edu
Computer Consultant
Office of Systems and Computing Services
Montana State University	Bozeman, MT	USA