>>>>> "Markus W" == mw  <mw@eunet.ch> writes:

Markus W> Here's a description of what's in there: - lower generic
Markus W> maximum PSL to spl4(), thus allowing the fast_ser interrupt
Markus W> to get incoming characters without hardly ever being blocked
Markus W> out. I now run a steady 57.6k PPP connection without any
Markus W> errors (no more silo-overflows..).  => this change affects
Markus W> drivers running off spl6, they'll run at spl4 now!  => I've
Markus W> stolen AUD3 interrupts for this purpose, expect troubles if
Markus W> you're using AUD3 interrupts for the intended purpose...  -
Markus W> generalized use of INTF_SOFTINT. Now replaced T_SSIR code.

I liked this a lot so I decided to try it out on my personal system
which by chance contains five INT6 devices (well 2 actually, but one
of them is the GoldenGateII bridge with four COM ports and an ethernet
card connected to it).  Besides these changes I also raised splimp to
spl4 and rebuilt from scratch.  I did this because I have had severe
problems with my ethernet interface running above splimp, and
si_callbacks haven't quite solved my problems.  Anyway, I also have a
Zeus SCSI interface, and this is what breaks.  First I thought some
interrupts got missed so I rewrote _fake_lev6intr to be a loop like
this:

_lev4intr:
_fake_lev6intr:	
	moveml	d0/d2/a0,sp@-		| save scratch regs
	/*
	 * check for fake level 6
	 */
	INTREQRADDR(a0)
	movew	a0@,d0
	btst	#INTB_EXTER,d0
	beq	Lplainintr		| if regular level 4, handle normally

Lcheckintr6:	
#if NZSSC > 0
	jbsr	_siopintr6		| check for siop (53C710) interrupt
	movl	d0,d2
#endif
#if NGGBUS > 0
	jbsr	_ggbusintr6		| check for GoldenGate interrupt
	addl	d0,d2
#endif
#if NCROSS > 0
	jbsr	_crossintr6		| check for CrossLink interrupt
	addl	d0,d2
#endif
	CIABADDR(a0)
	movb	a0@(CIAICR),d0		| read irc register (clears ints!)
	btst	#0,d0			| timerA interrupt?
	jeq     Lskipciab		| no
	lea	sp@(16),a1		| get pointer to PS
	movl	a1,sp@-			| push pointer to PS, PC
	jbsr	_hardclock		| call generic clock int routine
	addql	#4,sp			| pop params
	addql	#1,_intrcnt+28		| add another system clock interrupt
	jra	Lcheckintr6		| check if interrupts still pending
Lskipciab:
	tstl	d2
	jne	Lcheckintr6		| check if interrupts still pending
	INTREQWADDR(a0)
	movew	#INTF_EXTER+INTF_AUD3,a0@ | clear EXTER | AUD3 in intreq
	INTENAWADDR(a0)
	movew	#INTF_SETCLR+INTF_EXTER,a0@ | reenable EXTER interrupts
	moveml	sp@+,d0/d2/a0		| restore scratch regs
	addql	#1,_cnt+V_INTR		| chalk up another interrupt
	jra	rei			| all done

Yeah, I changed Lnotdma to Lplainintr, but that shouldn't matter.  I
also removed the intreq clearing from the devices as I do it in
Lskipciab instead.  I have removed the INTF_AUD? intena resets in
cc.c.  However, this doesn't help.  My zeus refuses to mount the root
with a ENXIO, but all the config stuff went OK, so it has to be the
interrupt system that's messed up.  Michael, have you tried Markus'
changes?  Markus, anyone, ideas? 

BTW, the above code makes statclock (called from hardclock) panic at
times (when siop_debug is enabled), so I must be doing something
wrong.

I'm a bit tired at the moment, so I can't see things as clear as I
want to, maybe tomorrow I'll manage to solve it myself.  But I
thought I'd try to let other people work for me while I'm asleep :-)

Niklas

PS. Michael!  I have a phase mismatch during startup.  Is that
    something you want a report on or should I just not care.  It
    seems to work anyway (unless siop_debug >= 0x10 :-) ).

Niklas Hallqvist	Phone: +46-(0)31-40 75 00
Applitron Datasystem	Fax:   +46-(0)31-83 39 50
Molndalsvagen 95	Email: niklas@appli.se
S-412 63  GOTEBORG	WWW:   Here
Sweden