> These facts together make me think that the error must be in the
> buslogic of GVP's accelerator.  It guess they have a two 16bit
> registers which builds 32 bit data together when accessing 16bit
> mem.  I also guess they use these as a cache, but that the high-
> word of the cache doesn't get filled by a 24-bit odd-aligned
> access.  Unfortunately it seems to still be valid.  Why do I think
> this is the case?  Well, the bitfield operation succeeds, I have
> never seen it behave incorrectly, BUT the next read, however
> ordinary (longword-aligned plain movel)  that instruction is.  The
> piece I cannot fit in, is why the pagefault is a trigger.  Maybe
> the buslogic cache gets flushed and the next 24-bit access gets
> associated to a randomly filled register, where it normally
> wouldn't change the cache a bit.  I don't know... Does anyone
> have any thoughts about my reasoning?

WOW! this is an awesome *cool* guess.  Hows this sound.

read data-part of the data falls across a page boundry-BUSERR
"cache" conatains the valid word and and *invalid* highword.  We go
pouncing along in trap() then vm_fault() finally reconstructing the
data and puting it in the stack frame to restart the operation.  Fine
the operation restarts and succeeds *however* the memory in the "cache"
is *not* updated with the data from the stack frame and so when the next
fetch grabs it its bogus.  Thats very vague on perpose I am sure there
is a more technical and better explanation.

Can you test this?

Chris.

------------------------------------------------------------------------------