> So I went and got ad1980 specifications.  As I understand (which may be
> wrong...), the card needs a delay of 50ns (maximun) after a reset to be up
> again.  So I added that delay just after the reset register is written, and
> all problem have gone away.

> No more "code invalid" nor "codec busy".

> +	delay(50);

A 50 microsecod delay seems a little extravagent if the device only
claims to need 50ns.

Have you tried to find out how short a delay is needed?

It might only be necessary to do a read from the reset register address.
(this is necessary in order to flush the write through all the PCI
bridges).

50ns delay is only just over a single clock on a 33M PCI bus. So it is
probably possible to time this by doing a PCI access to an appropriate
address rather than attempting a software delay loop.

	David

-- 
David Laight: david@l8s.co.uk