CVS commit: src/sys/arch/arm

["Matt Thomas" <matt%netbsd.org@localhost>]

Module Name:    src
Committed By:   matt
Date:           Fri Sep  7 11:49:00 UTC 2012

Modified Files:
        src/sys/arch/arm/arm: cpufunc.c cpufunc_asm_arm9.S cpufunc_asm_armv5.S
            cpufunc_asm_armv5_ec.S cpufunc_asm_sheeva.S
        src/sys/arch/arm/arm32: cpu.c fault.c genassym.cf
        src/sys/arch/arm/cortex: pl310.c pl310_reg.h
        src/sys/arch/arm/include: armreg.h cpu.h cpufunc.h
        src/sys/arch/arm/include/arm32: pmap.h
Added Files:
        src/sys/arch/arm/cortex: pl310_var.h

Log Message:
Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7


To generate a diff of this commit:
cvs rdiff -u -r1.114 -r1.115 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_arm9.S
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/arm/cpufunc_asm_armv5.S
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/arm/cpufunc_asm_armv5_ec.S
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/arm/cpufunc_asm_sheeva.S
cvs rdiff -u -r1.85 -r1.86 src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.84 -r1.85 src/sys/arch/arm/arm32/fault.c
cvs rdiff -u -r1.53 -r1.54 src/sys/arch/arm/arm32/genassym.cf
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/pl310.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/pl310_reg.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/pl310_var.h
cvs rdiff -u -r1.63 -r1.64 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.72 -r1.73 src/sys/arch/arm/include/cpu.h
cvs rdiff -u -r1.57 -r1.58 src/sys/arch/arm/include/cpufunc.h
cvs rdiff -u -r1.109 -r1.110 src/sys/arch/arm/include/arm32/pmap.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.