> This may have something to do with the stupid 8K fifo on the board.
> During a DMA write, the FIFO will slurp up all of the data in one go.
> I find that I get an interrupt indication when the DMA is complete,
> yet there are bytes in the fifo that have not been sent to the SCSI
> bus.

So why do you have to wait?  In what sense is the write not complete,
as far as you're concerned, at that point?  Do you have to wait for the
FIFO to drain before issuing another request or something?  I must be
missing something....

					der Mouse

			    mouse@collatz.mcrcim.mcgill.edu