> On Wed, 15 Sep 1999 01:07:42 -0700 (PDT) 
>  Todd Whitesel <toddpw@best.com> wrote:
>
>  > Which Alpha systems are you thinking of here? I know that at least the
>  > AXPvme boards have lots of distinct interrupt mask bits, and the PALcode
>  > uses them to simulate real numbered interrupt levels.
>

Sadly, the OSF/1 palcode throws away lots of nice alpha interrupt handling
hardware. All the cpu's provide nice hardware support for 15 different
software interrupt requests, but the osf/1 palcode throws every last one
away.

It maps all the HW interrupt levels down to exactly TWO for devices, and
then doesn't give us an API to program them, even thought they are a SW
(palcode) construct to begin with. (On the '164, the HW interrupts have
priorities, but SW, i.e. palcode, could remap them if it wanted.)

And without an API, it's hard to do anything intelligent with them, or even
know what they are going to be.  We do dispatch them at the two different
levels, but when blocking interrupts for critical sections, there isn't
much choice but to block the higher one.

	ross.harvey@computer.org